1. Field of the Invention
This invention relates to a semiconductor device having an extension structure and a method of fabricating thereof, which are particularly preferable as being applied to CMOS-structured semiconductor device.
2. Description of the Related Art
Many conventional MOS transistors employ LDD structure in order to suppress short channel effect and to improve hot-carrier resistance.
On the other hand, a major stream towards higher shrinkage and higher integration has been shortening gate length of MOS transistors. Shortening of the gate length, however, tends to raise nonconformities such as time-dependent changes in the threshold voltage due to hot carriers and degradation of mutual conductance. As one solution for the problem, a MOS transistor having so-called extension structure (LDD structure) has been proposed. This MOS transistor has a pair of impurity-diffused layers which are fabricated by forming shallow extension layers, forming side walls or the like as being attached to a gate electrode, and then forming deeper source and drain regions so as to partially overlap the extension region.
Recent accelerated trends towards still higher shrinkage and still higher integration of MOS transistors have, however, raised two following problems in those having the extension structure.
(1) Control of concentration profile in the extension region adds importance in pursuit of further shrinkage of MOS transistors. In particular, lateral concentration profile in the extension region holds the key for raising current drivability. In this case, roll-off characteristic of the threshold voltage and the current drivability, that is, electric resistance of the extension region, are in a relation of tradeoff, which demands precise adjustment of the both as described below.
To improve roll-off characteristic of the threshold voltage, it is preferable to ensure a metallurgical effective gate length as long as possible with respect to a given physical gate length. This successfully lowers impurity concentration of the channel, which raises mobility of carriers since they become less likely to be scattered by the impurity, and consequently improves current drivability of the MOS transistor. If the metallurgical gate length is kept constant, the physical gate length can be reduced.
On the other hand, the extension region should overlap the gate electrode to a sufficient degree. Since carrier density in an inverted layer under strong inversion condition could reach as high as an order of 1019/cm3, a portion of the extension region just under the edge of the gate electrode, that is, end portion of the extension region, may function as an electric resistor and may thus degrade the current drivability. To suppress such nonconformities, it is necessary to raise impurity concentration at the end portion to at least as high as 5×1019/cm3.
To form the extension region having thus-controlled impurity concentration, it is necessary to sharpen the lateral concentration profile in the extension region. More specifically, it is preferable to form a concentration profile ensuring an impurity concentration of 5×1019/cm3 or above for the end portion, and allowing it to sharply decrease from the end portion towards the channel. One ideal solution is to form the extension region in a so-called box shape. It is, however, extremely difficult to desirably control the sharpness in the profile since the lateral concentration profile is generally governed by diffusion phenomenon.
(2) Many of recent MOS transistors have a pocket region formed therein so as to surround the extension region by implanting impurity ion having a conductivity type opposite thereto, in order to further improve roll-off characteristic of the threshold voltage and current drivability. In a typical case of CMOS transistor, nMOS transistor uses indium (In) and PMOS transistor uses arsenic (As) or antimony (Sb) as the impurity to be contained in the pocket region, where all of which are relatively heavy elements.
These impurities are used because they are excellent in terms of upgrading the roll-off characteristic and current drivability. They are, however, heavy elements and thus causative of crystal defects when they are introduced by ion implantation, which defects cannot completely be removed even after annealing for activation, and tend to increase drain leakage, especially its component around the gate electrode. Since the pocket region is designed so as to be hidden behind deep source and drain regions, the gate peripheral thereof will remain almost constant. While annealing for clearing defects is known to be effective for suppressing the drain leakage current, the annealing also promotes diffusion of the impurities, which interferes shrinkage of the device.
As described in the above, an effort to further shrink the extension-structured MOS transistors undesirably makes it difficult to control the lateral concentration profile in the extension region, and an additional effort to form the pocket region aimed at improving roll-off characteristic of the threshold voltage and current drivability through reduction in drain leakage current undesirably makes it difficult to shrink the device, which is against the major purpose of the process.